Dear Candidate,
Warm Greetings to you!
It is to bring to your notice that we at Modernize Chip Solutions Pvt. Ltd ! (Gachibowli, Hyderabad) would like to have the privilege of hiring experienced candidates. Currently, we are having openings for RTL DESIGN Engineers (2+Experienced) that may be interested candidates.
We are hiring for RTL DESIGN Engineers (2+Experienced) who can join immediately.
Total Open Positions: 20
Name of Position: RTL DESIGN Engineer
Payroll Company Name: Modernize Chip Solutions(

Below is the screening criteria

Qualification Requirements: 2 – 5 years of solid experience in digital front-end or FPGA design Expertise in RTL coding in Verilog / VHDL/SV Familiarity with various bus protocols like AHB , AXI. Experience in CDC checks and waiver creation. Expertise in Perl, TCL language is a plus. Work experience in FPGA based design is an advantage.
Education Requirements: Required: Bachelor’s in Computer Engineering, Computer Science , Electrical Engineering, and / or related field Preferred: Master’s in Computer Engineering, Computer Science , Electrical Engineering, and/ or related field
Technical Skills Required: RTL Design, integration, quality checks like lint,
CDC, synthesis, upf.
Clients: We are with multiple clients. they are intel, Qualcomm, micron, western digital.
Package: will be decided based on your performance in interview.
Roles and Responsibilities: RTL / Digital design engineers will design and implement SoC, Peripherals, Modem, Bus and Network on-chip cores.
These candidates will understand and work on all aspects of the VLSI development cycle such as architecture, microarchitecture, Synthesis and design convergence and actively work with various core, verification, and design teams across multiple sites. They will perform RTL design, synthesis, timing analysis, lint check, clock domain crossing check.
Location: Willing to work in Bangalore, Hyderabad, locations (client locations)
If you are interested please reply with an updated CV to WhatsApp 7670849921 or [email protected]

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