RISC-V International Ratifies 15 New Specifications For RISC-V Designs

New Vector, Scalar Cryptography and Hypervisor specifications will help accelerate the adoption of RISC-V across a variety of market segments

In a step that will open new avenues for AI, ML and IoT application developers, RISC-V International, a global open hardware standards organisation has ratified 15 new specifications – representing more than 40 extensions – for the free and open RISC-V instruction set architecture (ISA). 
Included in the list are Vector, Scalar Cryptography and Hypervisor specifications. 

Vector Specification

The RISC-V Vector specification allows companies to easily customise RISC-V solutions for several edge computing applications from consumer IoT devices to industrial ML applications. 
With the ratification of the RISC-V Vector, developers can now accelerate the computation of data-intensive operations like ML inference for audio, vision and voice processing quickly and with low latency.
“The new RISC-V Vector specification will change the way people think about vector designs,” said Dave Ditzel, Founder and Executive Chairman of Esperanto Technologies. “With just over 100 instructions, the extension offers a simple and elegant approach to efficiently process the latest machine learning algorithms.” 

Hypervisor Specification

For virtual machine implementations, the RISC-V Hypervisor specification is required for hosting guest operating systems atop a type-1 or type-2 hypervisor. 
The Hypervisor ratification will help drive RISC-V adoption in the cloud and embedded applications such as data centres, automotive applications and industrial control applications where virtualisation is critical.  
Using the new specification, KVM and other open-source Virtual Machines have been ported on top of simulators by the RISC-V community.
“RISC-V has immense potential for the data centre, thanks to its flexibility, scalability and extensibility. The new RISC-V Hypervisor specification is a key piece in accelerating the adoption of RISC-V in data centre and desktop environments enabling virtualisation capabilities,” said Mark Himelstein, CTO of RISC-V International.

Scalar Cryptography Specification

The RISC-V Scalar Cryptography specification accelerates cryptographic workloads for small footprint deployments. These extensions allow secure and efficient accelerated cryptography in IoT and embedded devices. 
“The RISC-V Scalar Cryptography extensions allow for implementing standard cryptographic hash and block cipher algorithms that are an order of magnitude faster than using standard instructions in some cases. With RISC-V’s transparent and open approach, anyone can efficiently implement critical cryptographic algorithms in any class of CPU,” said Ben Marshall, Cryptographic Hardware Engineer at PQShield and member of the RISC-V Technical Steering Committee. 
“In addition to the performance benefits, these new extensions are very cheap to implement so companies can integrate popular cryptography algorithms in even the smallest connected devices.”
“In 2021, RISC-V International made huge leaps in our technical progress as we ratified 15 specifications that are critical for the future of computing,” said Krste Asanović, Chair of the RISC-V International Board of Directors. “The development of these specifications showcased the incredible benefits of open collaboration across companies and geographies as members worked together to develop novel approaches for the latest computing requirements.”