Design Verification Engineer for IP development team.
Position is based in Bangalore, part of Cadence IP Group.
Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C)
UVM testbench development to build a robust, scalable, and efficient testbench to verify the design IPs.
In addition to UVM functional verification, the role could involve Formal verification of complex design modules.
In addition to UVM functional verification, the role could involve participating in Emulation qualification of design IPs.
Understand the design and produce a detailed verification strategy and test plan.
Self-starter and learner with a passion for getting the job done on time with great quality.
Strong problem solving, analytical and debugging skills
Excellent verbal and written communications skills
Clearly communicate project status, issues, etc.
BE/BTech/ME/MTech – Electrical / Electronics / VLSI with an experience as a design and verification engineer.
Strong background in functional verification fundamentals, environment planning, test plan generation, environment development is a must.
Design Verification experience verifying complex designs and leading projects from concept to verification closure.
Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
Experience working on verifying any Serial IP or Interface protocols (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C)
Formal verification and/or Emulation experience is highly desirable.
AMBA protocol (AXI5, CHI, CXS) experience is desirable.
Familiarity with using 3rd party VIPs, Cadence preferred.
Team player with strong communication skills, and the ability to work independently on the verification of a portion of the design.
Prior experience in IP development teams would be an added advantage.
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