In this position, you will participate in standard cell layout development and delivery for corporate standard cell libraries for use in designs of Intels SoCs microprocessors, etc Responsibilities include but are not limited to Understanding of standard cell architecture Design of standard cell layouts Optimization of standard cell layouts considering area, performance, reliability tradeoffs Verification of layouts for design and architecture rules Understanding and implementation of DFM and ESD guidelines Understanding of RC delay electro migration self-heating and coupling capacitance Ability to recognize failure prone layout structures and produce robust layouts Equivalence verification of layouts with respect to schematics Development of automation for library design quality checking and reliability verification Release verification and handoff. Candidate must possess excellent written and verbal communication skills, strong team orientation, and ability to work in a flexible manner realigning to latest schedule requirement as needed
MS/ME/MTech in VLSI or BS/BE/BTech in Electronics Engineering with a minimum of three years of industry experience in designing and optimizing VLSI layout at the cell and or block level on different silicon process technologies is required.
Additional Desired Qualifications Knowledge of CAD layout tools eg Cadence Virtuoso Synopsys Custom Compiler any other industry-standard layout development tool
Experience using design rule checkers and layout verification tools
Knowledge of additional layout automation capabilities eg process shift
Knowledge of scripting languages TCL Perl Skill Python for design automation is a plus
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